In fabrication of semiconductor devices, standard cells are the building blocks of design logic. However, reducing a resulting size of standard cells requires a logic scaling of features, which is restricted, particularly for 20 nm technology nodes and beyond. This in turn results in loss of power, performance, and leakage. However, traditional methods use differing active region sizes to optimize transistor sizing that prevents effective logical scaling of features for standard cells. In advanced nodes such as 20 nm and 14 nm with finfet transistors, the device sizes are quantized, and circuit power, performance, and leakage need to be optimized by selecting the number of fins which are appropriate for a given circuit. However, removing dummy fins from active fins might risk patterning and etching, which can lead to more fin variations.
A need therefore exists for methodology enabling a optimization of the number of fins for a circuit, and the resulting device.